The present invention relates to a signal bus which is suitable for use in information processing apparatuses, and more particularly to a bus to which a plurality of signal processing means implemented in semiconductor integrated circuits or the like are connected.
Buses currently used in an information processing apparatus such as a personal computer, work station, and so on are designed to accomplish fast data transfer. As the use of a multi-processor becomes popular and a larger number of I/O devices are employed, the number of circuits connected to a bus are also increased. FIG. 2 shows an example of a conventional bus configuration which includes a bus connecting line 1; a bus driver 2; a bus receiver 3; a bus transceiver 4-1; and semiconductor integrated circuits 10-1 to 10-5. A convention bus configuration is disclosed, for example, in Taguchi et al, "Comparison of small amplitude interfaces for bus systems for 100 MHz era", Nikkei Electronics, No. 591, Sep. 27, 1993, pp. 269-290.
As shown in FIG. 2, five semiconductor integrated circuits 10-1, 10-2, 10-3, 10-4, and 10-5 are connected to the bus connecting line 1 in this example. More specifically, the semiconductor integrated circuits 10-1 and 10-5 are respectively connected to opposite ends of the bus connecting line 1, while the semiconductor integrated circuits 10-2, 10-3, and 10-4 are connected to respective branch lines from the bus connecting line 1. A bus line portion between branch points at both ends is called "a main line", and a line portion from each branch point to an associated one of the semiconductor integrated circuits 10-1 to 10-5 is called a "stub".
The semiconductor integrated circuits 10-2 to 10-5 are provided with bus transceivers 4-1 to 4-5, respectively, each having the bus receiver 2 and the bus driver 3. Data communications among these semiconductor integrated circuits 10-1 to 10-5 are performed through the bus connecting line 1 and the bus transceivers 4-1 to 4-5. It should be noted that while an example of a bus configuration having five semiconductor integrated circuits connected thereto has been explained, a multiplicity of similar bus lines are generally provided in accordance with the width of a bus required for a particular purpose.
If a bus line as described above is used for data transfer, for example, at an operating frequency of 30 MHz or more, wave distortion may occur in signals transferred on the bus connecting line 1, thus rendering semiconductor integrated circuits connected thereto more susceptible to erroneous operations. Main causes of this waveform distortion include load capacitances of the bus receivers 2 and the bus drivers 3 arranged in the semiconductor integrated circuits 10-1 to 10-5 and reflection of a signal caused by the branching of the bus connecting line 1. Specifically, while the bus connecting line 1 behaves as a distributed constant circuit in the above-mentioned operating frequency region, the branching of the bus connecting line 1 and the load capacitances cause the characteristic impedance of the bus line to be significantly disturbed, resulting in the waveform distortion in signals transferred on the bus connecting line 1. The branching and load capacitances also cause a lower signal propagation velocity, thereby limiting fast data transfer operations.
For example, when a bus line is formed on a printed circuit board made of glass epoxy resin, the characteristic impedance possessed by the bus line ranges approximately between 50 .OMEGA. and 100 .OMEGA.. However, if the bus line has branch lines, its characteristic impedance is decreased by one-half. Specifically, assuming that the characteristic impedance of the line is 100 .OMEGA., the branch lines cause the characteristic impedance to decrease to 50 .OMEGA.. In this case, a reflection coefficient is -1/3 at a branch point, so that about 33 percent of a negative reflection wave is generated as a backward pulse. Also, on a stub which is a line from a branch point to an associated semiconductor integrated circuit, if the ends of the stub are not terminated, a signal on the stub is repeatedly reflected at both ends of the stub, since the reflection coefficient on the semiconductor integrated circuit side is substantially one, thus requiring a long time until the signal waveform is settled in the entire system. Specifically, a time required for the waveform to settle is approximately double a signal propagation time through the largest distance on a bus line from one end to the other.
A signal propagation velocity Vp on a main line is also slowed down by stubs branched therefrom and load capacitances. As mentioned above, the main line is defined as a line between the branch points furthest away from each other on a bus connecting line. Assuming a bus line connected with loads having capacitances at regular intervals, a signal propagation velocity Vp' slowed down by the capacitances is expressed by the following equation (1): EQU Vp'=Vp.multidot.(1+Cd/Co).sup.-1/2 ( 1)
where Cd is an increased capacitance of the bus line by a capacitance distributed at a unit line length, and Co is a capacitance of the line per unit length.
For example, with a bus line having semiconductor integrated circuits each having an input capacitance of 15 pF connected thereto at intervals of 3 cm, since the capacitance of the line per unit length ranges from Co to 1 pf/cm, the signal propagation velocity Vp' is slowed down to 0.4 Vp. Specifically, when eight semiconductor integrated circuits are connected to a bus of 30 cm in length, a settling time is approximately 7.5 nsec if the bus is terminated, and approximately 15 nsec if the bus is not terminated. Therefore, an upper limit of the operating frequency is restricted to 66 MHz with the terminated bus, and 33 MHz with the non-terminated bus, respectively. Generally speaking, a settling time of a waveform on a bus depends on the length of a bus and the number of loads connected to the bus. As a result, these factors have heretofore limited a fast data transfer capability of the bus.
Waveform distortion of signals and slower propagation velocity due to reflection as described above are made worse as an increased number of semiconductor integrated circuits are connected to a bus and as the operating frequency is higher, thus limiting any improvement in the operation performance of the bus.
Further, with the above-mentioned contact branch bus, it is difficult to realize so-called live insertion/withdraw, i.e., inserting and/or withdrawing, during operation, a semiconductor integrated circuit or a module including a semiconductor integrated circuit, into and/or from a bus, without adversely affecting other semiconductor integrated circuits connected to the same bus. This is because a module, to be connected to the bus, has static electricity which will destroy other semiconductor integrated circuits already connected to the bus, and also because a change in load capacitance due to insertion or withdrawal of the module results in largely distorted signal waveforms on the bus.